The role of make is to automatically maintain a set of files that have dependencies on each other.
Make is useful for:
compiling large software projects that requires long and complex compile commands, with several arguments. Using the
timestamp of each file, make can compile only those parts that have been changed. This feature is a real time-saver;
allowing the build process to be automatic so that the users can easily build-and-use a package;
Make has no knowledge of the internal format of the files it is operating on, instead it relies on an input file tipically
called makefile or Makefile to find out the set of tasks required for each file to be processed.
The basic format of such a makefile is as follows:
Don't forget the tab's. Make it quite picky about its makefile format: all commands must begin with tabs and not spaces.
Note 2:
The blank line is not required by the GNU make. However many other make-alike applications requires the blank line
so it is best to keep it for wider compatibility.
In order to be as practically as possible we will just comment on a makefile that can easily serve as a template:
# the list of object files to generate
OBJS = main.o a.o b.o
# this is the compiler;
CC = gcc
# arguments passed to the compiler
CFLAGS = -g -Wall
# this is the linker;
# on GNU systems the linker 'ld' is automatically called by the compiler
LD = gcc
# arguments passed to the linker
LDFLAGS =
# the name of the executable program
PROG_NAME = test
# the command used to delete files on the target system;
# on windows systems use 'del'
DELETE = rm -f
.PHONY: all clean install rebuild
all: $(PROG_NAME)
$(PROG_NAME): $(OBJS)
$(LD) $(OBJS) -o $(PROG_NAME)
main.o: main.c
$(CC) $(CFLAGS) -c main.c
a.o: a.c a.h
$(CC) $(CFLAGS) -c a.c
b.o: b.c b.h
$(CC) $(CFLAGS) -c b.c
clean:
$(DELETE) $(PROG_NAME) $(OBJS)
install:
cp $(PROG_NAME) /home/razvan/bin
rebuild: clean all
The above makefile contains the following elements:
dependencies: $(OBJS), main.c, a.c, a.h, b.c, b.h, clean, all
commands: $(LD) $(OBJS) -o $(PROG_NAME)
Definitions:
variable: a make variable is a string that can be expanded with the syntax $(VARIBLE) or ${VARIABLE}
target: a target is a file that should be generated.
phony target: the name of a task. For example, most makefiles have a phony target called "install".
You can specify a (phony) target on the invokation of make.
dependencies: a dependecy is a target (a.k.a. file) or a phony target.
command: a sequence of shell commands to be executed.
Note 1:
A target can be a dependency for some other target.
Note 2:
A command will not be shown as it is executed if it is preceeded by the @ character.
Example:
install:
@cp $(PROG_NAME) /home/razvan/bin
This is a pretty introductory chapter to make. As my knowledge on the matter will advance I may update this article.
However this subject is outdated because a new tool is in the arsenal of programmers nowadays: automake.
With this tool it is possible to automatically generate make files. Automake can deal with one of the biggest drawbacks of make:
manual editing of dependencies. Good knowledge of make is desirable but mastering automake should take higher precedence.